ARM Cortex-A72

Central processing unit
  • 1–4 per cluster, multiple clusters[1]
Products, models, variantsProduct code name(s)
  • Maya
HistoryPredecessor(s)ARM Cortex-A57Successor(s)ARM Cortex-A73

The ARM Cortex-A72 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Austin design centre. The Cortex-A72 is a 3-way decode out-of-order superscalar pipeline.[1] It is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC). The Cortex-A72 was announced in 2015 to serve as the successor of the Cortex-A57, and was designed to use 20% less power or offer 90% greater performance.[2][3]

Overview

  • Pipelined processor with deeply out-of-order, speculative issue 3-way superscalar execution pipeline
  • DSP and NEON SIMD extensions are mandatory per core
  • VFPv4 Floating Point Unit onboard (per core)
  • Hardware virtualization support
  • Thumb-2 instruction set encoding reduces the size of 32-bit programs with little impact on performance.
  • TrustZone security extensions
  • Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution
  • 32 KiB data (2-way set-associative) + 48 KiB instruction (3-way set-associative) L1 cache per core
  • Integrated low-latency level-2 (16-way set-associative) cache controller, 512 KB to 4 MB configurable size per cluster
  • 48-entry fully associative L1 instruction translation lookaside buffer (TLB) with native support for 4 KiB, 64 KiB, and 1 MB page sizes
  • 32-entry fully associative L1 data TLB with native support for 4 KiB, 64 KiB, and 1 MB page sizes
    • 4-way set-associative of 1024-entry unified L2 TLB per core, supports hit-under-miss
  • Sophisticated branch prediction algorithm that significantly increases performance and reduces energy from misprediction and speculation
  • Early IC tag –3-way L1 cache at direct-mapped power*
  • Regionalized TLB and μBTB tagging
  • Small-offset branch-target optimizations
  • Suppression of superfluous branch predictor accesses

Chips

See also

References

  1. ^ a b "Cortex-A72 Processor". ARM Holdings. Retrieved 2014-02-02.
  2. ^ Frumusanu, Andrei (3 February 2015). "ARM Announces Cortex-A72, CCI-500, and Mali-T880". Anandtech. Retrieved 29 March 2017.
  3. ^ Frumusanu, Andrei (23 April 2015). "ARM Reveals Cortex-A72 Architecture Details". Anandtech. Retrieved 29 March 2017.
  4. ^ "Raspberry Pi 4 on sale now from $35". Raspberry Pi. 2019-06-24. Retrieved 2019-06-24.

External links

  • Official website
  • ARM Cortex-A72 Technical Reference Manuals
  • v
  • t
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Application ARM-based chips
Application
processors
(32-bit)
ARMv7-A
Cortex-A5
Cortex-A7
Cortex-A8
Cortex-A9
Cortex-A15
Cortex-A17
Others
ARMv7-A
compatible
ARMv8-A
Others
Application
processors
(64-bit)
ARMv8-A
Cortex-A35
Cortex-A53
Cortex-A57
Cortex-A72
Cortex-A73
  • Qualcomm Snapdragon 460, 636, 660, 632, 662, 665, 680, 685, 835
  • Samsung Exynos 7872, 7884, 7885, 7904, 9609, 9610, 9611
  • HiSilicon Kirin 710, 960, 970
  • MediaTek MT6771/V, MT6799, MT8183, MT8788
  • Amlogic S922X
Others
ARMv8-A
compatible
ARMv8.1-A
ARMv8.1-A
compatible
ARMv8.2-A
Cortex-A55
Cortex-A75
Cortex-A76
Cortex-A77
Cortex-A78
Cortex-X1
Neoverse N1
Others
  • Cortex-A65, Cortex-A65AE, Cortex-A76AE, Cortex-A78C, Cortex-X1C, Neoverse E1
ARMv8.2-A
compatible
ARMv8.3-A
ARMv8.3-A
compatible
ARMv8.4-A
Neoverse V1
ARMv8.4-A
compatible
ARMv8.5-A
ARMv8.5-A
compatible
ARMv8.6-A
ARMv8.6-A
compatible
ARMv9.0-A
Cortex-A510
Cortex-A710
Cortex-A715
Cortex-X2
Cortex-X3
Neoverse N2
Neoverse V2
ARMv9.2-A
Cortex-A520
  • Qualcomm Snapdragon 7+ Gen 3, Snapdragon 8(s) Gen 3
  • Samsung Exynos 2400
Cortex-A720
Cortex-X4
Neoverse N3
-
Neoverse V3
-