MCST-R1000

PerformanceMax. CPU clock rate750 MHz to 1 GHzFSB speeds2 GbpsCacheL1 cache48 KBL2 cache2 MBArchitecture and classificationApplicationEmbeddedTechnology node100 mm²Instruction setSPARC V9Physical specificationsCoresPackage(s)HistoryPredecessor(s)MCST-R500SSuccessor(s)MCST-R2000

The MCST R1000 (Russian: МЦСТ R1000) is a 64-bit microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.^[2]

During development this microprocessor was designated as MCST-4R.^[1]

MCST R1000 Highlights

• implements the SPARC V9 instruction set architecture (ISA)
• quad-core
• core specifications:
  • in-order, dual-issue superscalar
  • 7-stage integer pipeline
  • 9-stage floating-point pipeline
  • VIS extensions 1 and 2
  • Multiply–accumulate unit
  • 16 KB L1 instruction cache (parity protection)
  • 32 KB L1 data cache (parity protection)
  • size 7.6 mm²
• shared 2MB L2 cache (ECC protection)
• integrated memory controller
• integrated ccNUMA controller
• 1 GHz clock rate
• 90 nm process
• die size 128 mm²
• ~150 million transistors
• power consumption 15W

References