Millicode

Higher level of microcode

Program execution
General concepts
Code Translation Compiler Compile time Optimizing compiler Intermediate representation (IR) Execution Runtime system Runtime Executable Interpreter Virtual machine
Types of code
Source code Object code Bytecode Machine code Microcode
Compilation strategies
Ahead-of-time (AOT) Just-in-time (JIT) Tracing just-in-time Compile and go system Precompilation Transcompilation Recompilation
Notable runtimes
Android Runtime (ART) BEAM Common Language Runtime (CLR) and Mono CPython and PyPy crt0 Java virtual machine (JVM) LuaJIT Objective-C and Swift's V8 and Node.js Zend Engine
Notable compilers & toolchains
GNU Compiler Collection (GCC) LLVM and Clang MSVC
v t e

In computer architecture, millicode is a higher level of microcode used to implement part of the instruction set of a computer. The instruction set for millicode is a subset of the machine's native instruction set, omitting those instructions that are implemented using millicode, plus instructions that provide access to hardware not accessible using the native instruction set. Millicode routines are used to implement more complex instructions visible to the user of the system. Implementation of millicode requires a special processor mode called millimode that provides its own set of registers, and possibly its own special instructions invisible to the user.^[1]

IBM invented both the concept and the term millicode for the System/390 9672-G4 processor in 1997.^[1] The following are cited as advantages of millicode:^[1]

More complex instructions can easily be constructed from several millicode instructions.
Construction of a compatible line of computer models with different performance is simplified.
Millicode instructions can bypass CPU cache to improve performance.
Instructions can update multiple storage locations without concern for being interrupted.
Millicode can execute instructions at a higher privilege level without involving the operating system.
Millicode can provide a complex instruction as if it were a subroutine, making user code smaller.

The "i370" code for the "Capitol" chipset used in some ES/9370 models was similar to millicode, in that it was written as a combination of System/370 instructions and code that had access to special hardware features.^[2]

References

^ ^a ^b ^c Rogers, Bob (Sep–Oct 2012). "The What and Why of zEnterprise Millicode". IBM Systems Magazine. Archived from the original on October 9, 2012.
^ Wilhelm Spruth, ed. (6 December 2012). "7.2 High Level Microprogramming in I370". The Design of a Microprocessor. Springer-Verlag. ISBN 978-3-642-74918-6.

External links

Rogers, Robert. "The What and Why of System z Millicode" (PDF). SHARE, Summer 2012. Retrieved January 25, 2013.

Processor technologies

Models

Architecture

Instruction set
architectures

Types	Orthogonal instruction set CISC RISC Application-specific EDGE TRIPS VLIW EPIC MISC OISC NISC ZISC VISC architecture Quantum computing Comparison Addressing modes
Instruction sets	Motorola 68000 series VAX PDP-11 x86 ARM Stanford MIPS MIPS MIPS-X Power POWER PowerPC Power ISA Clipper architecture SPARC SuperH DEC Alpha ETRAX CRIS M32R Unicore Itanium OpenRISC RISC-V MicroBlaze LMC System/3x0 S/360 S/370 S/390 z/Architecture Tilera ISA VISC architecture Epiphany architecture Others

Execution

Instruction pipelining	Pipeline stall Operand forwarding Classic RISC pipeline
Hazards	Data dependency Structural Control False sharing
Out-of-order	Scoreboarding Tomasulo's algorithm Reservation station Re-order buffer Register renaming Wide-issue
Speculative	Branch prediction Memory dependence prediction

Parallelism

Level	Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory Distributed
Multithreading	Temporal Simultaneous Hyperthreading Simultaneous and heterogenous Speculative Preemptive Cooperative
Flynn's taxonomy	SISD SIMD Array processing (SIMT) Pipelined processing Associative processing SWAR MISD MIMD SPMD

Processor
performance

Transistor count
Instructions per cycle (IPC)
- Cycles per instruction (CPI)
Instructions per second (IPS)
Floating-point operations per second (FLOPS)
Transactions per second (TPS)
Synaptic updates per second (SUPS)
Performance per watt (PPW)
Cache performance metrics
Computer performance by orders of magnitude

Types

By application	Embedded system Microprocessor Microcontroller Mobile Ultra-low-voltage ASIP Soft microprocessor
Systems on chip	System on a chip (SoC) Multiprocessor (MPSoC) Cypress PSoC Network on a chip (NoC)
Hardware accelerators	Coprocessor AI accelerator Graphics processing unit (GPU) Image processor Vision processing unit (VPU) Physics processing unit (PPU) Digital signal processor (DSP) Tensor Processing Unit (TPU) Secure cryptoprocessor Network processor Baseband processor

Word size

Core count

Components

Functional units	Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Memory management unit (MMU) Load–store unit Translation lookaside buffer (TLB) Branch predictor Branch target predictor Integrated memory controller (IMC) Memory management unit Instruction decoder
Logic	Combinational Sequential Glue Logic gate Quantum Array
Registers	Processor register Status register Stack register Register file Memory buffer Memory address register Program counter
Control unit	Hardwired control unit Instruction unit Data buffer Write buffer Microcode ROM Counter
Datapath	Multiplexer Demultiplexer Adder Multiplier CPU Binary decoder Address decoder Sum-addressed decoder Barrel shifter
Circuitry	Integrated circuit 3D Mixed-signal Power management Boolean Digital Analog Quantum Switch